Method for Reducing Overdrive Need in MOS Switching and Logic Circuit

ABSTRACT

The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

TECHNICAL FIELD

The present document relates to electronic switching and logic circuits.In particular, the present document relates to lowering the signal rangebelow system supply range.

BACKGROUND

Switching and logic circuits provide waveforms which are the result ofoperations upon one or more input signals.

The current practice for this type of circuits is to operate them atfull, range of available supply. The power consumption of such a circuitcan be expressed by:

P _(dyn) =C _(L) ×V ² ×f×α

from which it is apparent that the power consumption of such circuitsdepends quadratically on the supply value (V), and linearly oncapacitive load (C_(L)), frequency of operation (f), and activity factor(α). The activity factor defines the ratio of the actual average numberof transitions per second, divided by the maximum number of the same.

The disadvantage of this practice is the use of full supply rangeleading to unnecessarily high power consumption.

SUMMARY

A principal object of the present disclosure is to achieve signalamplitude swing of switching and logic circuits independent of supplyrange.

A further principal object of the disclosure is to achieve a poweroptimum amplitude swing depending upon frequency, activity factor,technology characteristics (load of the structures, drive strength ofactive devices) as constraints.

A further object of the disclosure is to realize a whole family of logiccircuits based on supply reduction and AC coupling concepts.

A further object of the disclosure is to increase speed and drivestrength of switching and logic circuits.

A further object of the disclosure is to realize amplifiers/attenuators,both digitally and analogically controlled, based onprogression/modulation in the signal swing from stage to stage.

In accordance with the objects of this disclosure a method to lowersignal range of a switching and logic circuits below supply range inorder to optimize amplitude swing in regard of power consumption hasbeen achieved. The method disclosed comprises the steps of: (1)providing a switching or logic circuit with positive and negative supplyrails comprising one or more stages, (2) lowering the signal range belowthe supply range by adding for each circuit stage one or two genericdevice networks, wherein each generic device network establishes avoltage drop between the circuit and an associated supply rail, whereinthe signal swings between a positive reference voltage, provided by thevoltage drop in regard of the positive supply rail, and a negativereference voltage, provided by the voltage drop in regard of thenegative supply rail, and wherein each of the voltage drops is constantand is independent of current flowing through the generic devicenetwork, (3) decoupling the signal range from biasing voltages byproviding a DC biasing network comprising biasing voltage sourcesproviding biasing voltages as required and corresponding resistorsproviding impedances required, and (4) providing AC signal coupling ofactive devices of the circuit by a capacitive network.

In accordance with the objects of this disclosure a switching or logiccircuit comprising one or more stages configured to a signal range belowsupply range in order to optimize amplitude swing in regard of powerconsumption has been achieved. The circuit disclosed comprises: one ortwo generic device networks implemented for each stage of the circuitadapted each to providing a positive and/or a negative reference voltagefor each stage of the circuit while the reference voltages allow asignal range of each stage of the circuit below the supply range of thecircuit, wherein the reference voltages are constant and independent ofcurrents flowing through the one or two generic device networks of eachstage, a DC biasing network biasing active devices of the circuitcomprising biasing voltage sources providing biasing voltages asrequired and resistors providing impedances for biasing as required, andan AC coupling network of capacitive means to couple AC signals of astage to a neighboring stage; wherein the DC biasing network and the ACcoupling network are enabled to allow a signal range which may be lowerthan threshold voltages of the active devices of the circuit.

BRIEF DESCRIPTION OF THE FIGURES

The invention is explained below in an exemplary manner with referenceto the accompanying drawings, wherein

FIG. 1 prior art depicts as example a logic inverter chain wherein anoutput signal of one stage is DC coupled to the input of a subsequentstage, and the signal range coincides to the available supply.

FIG. 2 depicts a logic inverter chain as example of the proposedinnovation

FIG. 3 illustrates generic pull up and pull down networks.

FIG. 4 shows an extension to support non constant voltage swings betweensubsequent stages.

FIG. 5 shows a flowchart of a method to lower a signal range ofswitching and logic and logic circuits below supply range in order tooptimize amplitude swing in regard of power consumption.

FIG. 6 shows for example a circuit diagram of a NAND logic componentshowing a pull-down network PD and a pull-up network PU.

DETAILED DESCRIPTION

Methods and circuits to achieve power optimum amplitude swing dependingupon frequency, activity factor, technology characteristics (load of thestructures, drive strength of active devices) as constraints by settingsignal amplitude swing independent of supply range are disclosed.

It should be noted that the disclosure is not only applicable to MOStechnology but also to all other technologies wherein one port is usedto control current flow through other ports, such as e.g. bipolar, JFET,and other technologies.

FIG. 1 prior art depicts, as example, a logic inverter chain, wherein anoutput signal of one stage is DC coupled to the input of a subsequentstage, and the signal range coincides to the available supply. Thisapproach has the disadvantages outlined above.

FIG. 2 depicts a logic inverter chain as example of the proposedinnovation, comprising:

-   -   a device voltage source V1 lifting the lower inverter rail to a        voltage above the reference of the embedding circuit;    -   a device voltage source V2 lowering the upper inverter rail to a        voltage below the supply of the embedding circuit;    -   a network (voltage source Vn, R2) providing a DC voltage to the        gates of the n-type devices 20, 23, and 25;    -   a network (voltage source Vp, R1) providing a DC voltage to the        gate of the p-type devices 21, 22, and 24;    -   a network C2 providing a means to couple the AC signal to the        input port of the n-type devices 20, 23, and 25; and    -   a network C1 providing a means to couple the AC signal to the        input port of the p-type device 21, 22, and 24.

Following the method of this example of FIG. 2, it is possible for thelogic devices 21-25 to swing between the levels defined by voltages V1and V2, while the load drive capability can be set independently byacting on Vp and Vn. The number of chain connected devices is arbitrary.The signal swing between V1 and V2 is obviously lower than a signalswing of prior art between V_(sup) and ground.

Also important are the means of biasing the active devices 20-25 throughvoltage sources Vp, and Vn, plus the resistors R1 and R2. The resistorsR1 and R2 are also important as they provide high impedance to thesignal but otherwise allow DC. Exceptionally voltage sources or theresistors could be omitted for some instances, but they are normallyrequired to achieve proper operation.

A coupling network, comprising in FIG. 2 capacitors C1 and C2, iscoupling the signals to the devices.20-25.

An important feature of the disclosure is that the voltages V1 and V2,generated by the generic device networks (voltage sources), areindependent of the currents flowing through them.

The elements pointed out in the example of FIG. 2: V1, V2, Vn, Vp, R1,R2, C1, and C2 are all essential for the most general operation of thedisclosure. Their function can be implemented, however, with a varietyof devices. For instance, voltage sources V1 or V2 can be an LDO, aDC/DC converter's output, a diode and so forth. The functions asdescribed in the example of FIG. 2 have to be provided.

In special cases, some of the parameters can be set to zero value.

For the sake of generalization, the example shown in FIG. 2 can beextended in the following ways:

A—Generic Pull-Up and Pull-Down Networks, and Connections Thereof.

FIG. 3 illustrates implementing generic device pull up and pull downnetworks. With reference to FIG. 3, a “generic device pull-up network”can be devised, able to establish a low ohmic connection between theoutput of the circuit and the positive reference, based on a fixedpattern of the input signals, generally called a Pull-up network, PU1and PU2.

Dually, a network providing a low ohmic path between the output of thecircuit and the negative reference is termed a generic device Pull-downnetwork, PD1 and PD2. A PU or PD can be established in many ways, e.g.by simple series/parallel device arrangements.

A generic device Pull-Up network (PU) network is a combination ofdevices able to tie the output of a stage to the upper reference voltageand accordingly a generic device Pull-Down network (PD) network is justa combination of devices able to tie the output of the stage to thelower reference voltage. Pull-Up really means “pull output to supply”and Pull-Down really means “pull output to ground”. However, in thecircuits of the present disclosure “supply” and “ground” are not thoseof the system, but especially created ones using the voltage sources ofthe generic devices network generating the upper reference voltage andthe lower reference voltage.

It should be noted that the voltage drops from supply rails to upper andlower circuit reference is established by the voltage sources V1 and V2,which we call “generic device networks”. A PU or PD can be establishedin many ways.

The nature of the generic device networks or generic devicePull-down/Pull-up network, doesn't have to be MOS nor complementary,other technologies such as e.g. bipolar, JFET, and other technologiesare also possible.

One key objective of the generalization in regard of generic devicePull-up and Pull-down networks, and connections thereof is to realize awhole family of logic circuits based on supply reduction and AC couplingconcepts. This family may include combinational and sequential, i.e.including memory elements. In digital circuit theory, combinationallogic (sometimes also referred to as combinatorial logic ortime-independent logic) is a type of digital logic which is implementedby boolean circuits, where the output is a pure function of the presentinput only. This is in contrast to sequential logic, in which the outputdepends not only on the present input but also on the history of theinput. In other words, sequential logic has memory while combinationallogic does not.

This family of logic circuits may comprise all standard logic componentssuch as e.g. AND, OR, INV, NAND, NOR, XOR, XNOR, plus memory elementssuch as Flip-Flops, etc., using technologies for example such as CMOS,TTL, ECL, etc. This includes also as non-limiting example passtransistor logic (PTL) as well, as for example latches and memoryelements. In electronics, pass transistor logic describes several logicfamilies used in the design of integrated circuits. It reduces the countof transistors used to make different logic gates, by eliminatingredundant transistors. Transistors are used as switches to pass logiclevels between nodes of a circuit, instead of as switches connecteddirectly to supply voltages.

FIG. 6 shows for example a circuit diagram of a NAND logic componentshowing a pull-down network PD and a pull-up network PU. The currentsources to generate voltages V1 and V2, which could be implemented inmany different ways, are indicated by dashed lines showing connectionsto supply VDD and ground (the AC connections are omitted). The outputsignal for the NAND logic component swings between V1 and V2. This NANDlogic component including PU and PD may be a member of the family oflogic components.

Returning to AC coupling concepts it is well known that transistors havethreshold voltages. They can be turned ON or OFF according to the valueof a voltage, between a controlling terminal and a reference terminal.If the value of this voltage is greater/lower than the threshold voltageV_(th), then the transistor allows/blocks flow of charge from its otherterminal to the reference terminal. It is therefore important to allowfor controlling signals to rise above and below the tech constantthreshold voltage V_(th). In most circuits at hand, for directinput-output coupling as in the Prior Art, this value of the voltagerises to the supply voltage. That is, it is not possible to lower supplyrange below (V_(th)+V_(ov)), where V_(ov) is needed to allow a targetcharge flow (drive strength).

However, decoupling the signal amplitude from the DC biasing asdescribed in the disclosure, allows for the signal swing, i.e. thereference-to-reference voltage, to be lower than V_(th), because themaximum signal present at the controlling port of the device is nowV_(bias)+V_(swing) and it is this new quantity that needs to reachV_(th)-V_(ov). This is of course much easier to achieve because voltageV_(bias) can be set as desired. V_(bias) corresponds to one of thevoltages V_(n), or V_(p) in FIG. 2.

B—Non Constant Supply Levels Between Stages

FIG. 4 shows an extension to support non constant voltage swing betweensubsequent stages. With reference to FIG. 4, a varying (decreasing orincreasing) biasing voltage scheme can be achieved for (V11, V12, V21V22, Vn1, Vn2, Vp1, and Vp2) between interconnected stages as to provideamplification or reduction of the power level associated with a certainsignal. Number of interconnected stages is arbitrary. The circuit may beobviously extended including V1 x, V2 x, Vnx, and Vpx.

One key objective of the generalization in regard of non-constant supplylevels between stages is to realize amplifiers/attenuators, bothdigitally and analogically controlled based on the method disclosed of aprogression/modulation in the supply range from stage to stage. Withreference to FIG. 4, a chain of stages can provide the desired powergain by setting the supply progression according to the nature of theincoming signal.

Furthermore it should be noted that the present disclosure enhancescircuit speed, because this is direct function of signal swing range,load to be driven, and current capability (drive strength) by providinga DC biasing network comprising biasing voltage sources providingbiasing voltages as required and corresponding resistors providingimpedances required

FIG. 5 shows a flowchart of a method to lower signal range of switchingand logic and logic circuits below supply range in order to optimizeamplitude swing in regard of power consumption.

A first step 50 depicts a provision of a switching or logic circuit withpositive and negative supply rails comprising one or more stages. Thenext step 51 shows lowering the signal range below the supply range byadding for each circuit stage one or two generic device networks,wherein each generic device network establishes a voltage drop betweenthe circuit and an associated supply rail, wherein the signal swingsbetween a positive reference voltage, provided by the voltage drop inregard of the positive supply rail, and a negative reference voltage,provided by the voltage drop in regard of the negative supply rail, andwherein each of the voltage drops is constant and is independent of acurrent flowing through the generic device networks. Step 52 isfollowing describing decoupling the signal range from biasing voltagesby providing a DC biasing network comprising biasing voltage sourcesproviding biasing voltages as required and corresponding resistorsproviding impedances required, and the last step 53 discloses providingAC signal coupling of active devices of the circuit by a capacitivenetwork.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A method to lower signal range of a switchingand/or logic circuit below supply range in order to optimize amplitudeswing in regard of power consumption, the method comprising the stepsof: (1) providing a switching or logic circuit with positive andnegative supply rails comprising one or more stages; (2) lowering thesignal range below the supply range by adding for each circuit stage oneor two generic device networks, wherein each generic device networkestablishes a voltage drop between the circuit and an associated supplyrail, wherein the signal swings between a positive reference voltage,provided by the voltage drop in regard of the positive supply rail, anda negative reference voltage, provided by the voltage drop in regard ofthe negative supply rail, and wherein each of the voltage drops isconstant and is independent of current flowing through the genericdevice networks; (3) decoupling the signal range from biasing voltagesby providing a DC biasing network comprising biasing voltage sourcesproviding biasing voltages as required and corresponding resistorsproviding impedances required; and (4) providing AC signal coupling ofactive devices of the circuit by a capacitive network.
 2. The method ofclaim 1, wherein each stage of the circuit comprises a generic devicePull-Down network (PD) and a generic device Pull-Up network (PU),wherein a Pull-Up network (PU) network is a combination of devices ableto tie the output of a stage to the upper reference voltage and aPull-Down network (PD) network is a combination of devices able to tiethe output of a stage to the lower reference voltage.
 3. The method ofclaim 1, wherein the AC coupling network and the DC biasing networkallow signal swings lower than threshold voltages of active devices ofthe circuit.
 4. The method of claim 1, wherein the method is used tobuild a family of combinational and sequential logic circuits.
 5. Themethod of claim 4, wherein the family of logic circuits includes passtransistor logic circuits.
 6. The method of claim 5, wherein the passtransistor logic circuits include latches and memory elements,
 7. Themethod of claim 4, wherein the family of logic circuits comprises AND,OR, INV, NAND, NOR, XOR, and XNOR logic circuits
 8. The method of claim1, wherein specific signal ranges for each circuit stage can be achievedby decreasing or increasing the voltage drop of the one or two genericdevice networks associated to the stage where the signal range should beadapted.
 9. The method of claim 1, wherein amplifiers/attenuators, bothdigitally and analogically controlled, are realized based onprogression/modulation in the supply range from stage to stage.
 10. Themethod of claim 1, wherein the circuit is a MOS circuit.
 11. The methodof claim 1, wherein the circuit is built using any of semiconductortechnologies wherein one port is used to control current flow throughother ports.
 12. The method of claim 1, further comprising definingdrive strength of the signals of the circuit by setting accordingly thebiasing voltages.
 13. A switching or logic circuit comprising one ormore stages configured to a signal range below supply range in order tooptimize amplitude swing in regard of power consumption comprising: oneor two generic device networks implemented for each stage of the circuitadapted each to providing a positive and/or a negative reference voltagefor each stage of the circuit while the reference voltages allow asignal range of each stage of the circuit below the supply range of thecircuit, wherein the reference voltages are constant and independent ofcurrents flowing through the one or two generic device networks of eachstage; a DC biasing network biasing active devices of the circuitcomprising biasing voltage sources providing biasing voltages asrequired and resistors providing impedances for biasing as required; andan AC coupling network of capacitive means to couple AC signals of astage to a neighboring stage; wherein the DC biasing network and the ACcoupling network are enabled to allow a signal range which may be lowerthan threshold voltages of the active devices of the circuit.
 14. Thecircuit of claim 13 wherein each stage of the circuit comprises ageneric device pull-down network (PD) and a generic device pull-upnetwork (PU), wherein a Pull-Up network (PU) network is a combination ofdevices able to tie the output of a stage to the upper reference voltageand a Pull-Down network (PD) network is a combination of devices able totie the output of a stage to the lower reference voltage.
 15. Thecircuit of claim 13 wherein the circuit is adapted to decoupling thesignal range from the DC biasing voltages by the DC biasing network andthe AC coupling network allowing a signal swing lower than a thresholdvoltage of active devices of the circuit.
 16. The circuit of claim 13wherein the circuit is a part of a family of combinational andsequential logic circuits.
 17. The circuit of claim 16 wherein thefamily of logic circuits includes pass transistor logic circuits. 18.The circuit of claim 17 wherein the pass transistor logic circuitsinclude latches and memory elements,
 19. The circuit of claim 16 whereinthe family of logic circuits comprises AND, OR, INV, NAND, NOR, XOR, andXNOR logic circuits.
 20. The circuit of claim 13 wherein specific signalranges for each circuit stage can be achieved by decreasing orincreasing the voltage drop of the one or two generic device networksassociated to the stage where the signal range should be adapted. 21.The circuit of claim 13 wherein drive strength of the signals of thecircuit are defined by setting accordingly the biasing voltages.
 22. Thecircuit of claim 13 wherein the circuit is a MOS circuit.
 23. Thecircuit of claim 13 wherein the circuit is built using any ofsemiconductor technologies wherein one port is used to control currentflow through other ports.